1. Field of the Invention
The present invention generally relates to alignment methods of chips. More specifically, the present invention relates to an alignment method of chips utilizing an alignment mark corresponding to a plurality of chips formed on a semiconductor wafer.
2. Description of the Related Art
Conventionally, in a case where a plurality of chips (dies) needed to undergo laser trimming are formed on a semiconductor wafer, techniques of aligning the chip provided with an alignment mark including materials such as metal with a laser light is known. According to the techniques, the alignment of the chip is performed by irradiating the alignment mark with the laser light, by detecting a peak of reflected waves from the alignment mark and by finding a position of the chip. In such alignment methods for trimming, in terms of a quick alignment, a multi-die alignment is performed. In the multi-die alignment, a plurality of chips in a certain area which can be trimmed continuously only with the laser moving are aligned in a block. More specifically, the multi-die alignment aligns the entire predetermined area once, by irradiating the alignment marks of a few chips at the corner of the predetermined area with the laser light and by detecting the reflected waves. This allows all of the chips in the predetermined area to be aligned in one block, which enables a manufacturer to perform the alignment in a short time. Also, when the multi-die alignment is performed regarding all of the dies in the predetermined areas in case proper reflected waves are not detected by irradiating the chips around the corner in the predetermined area with the laser, a process of changing into a single-die alignment is performed. In the single-die alignment, each of the chips (dies) is individually aligned so that the alignment is performed in an ensured manner.
Moreover, as a technique utilizing the multi-die alignments, in a case where a semiconductor chip formed on a surface of a substrate has a fuse for adjusting resistance, a first alignment mark including the same material as the fuse and a second alignment mark including material with a different reflectance from the first material, a trimming method with the alignment marks is disclosed in Japanese patent publication 2001-35924. In the trimming method, the trimming is performed by aligning the second alignment marks in a case when the first alignment with the first alignment marks fails.
In the trimming method disclosed in the Japanese patent publication 2001-35924r the first alignment marks including poly silicon, the same material as the fuses, are formed by the same mask, which allows the manufacturer to produce semiconductor devices without relative displacements and to make the alignment marks highly reliable. When the alignment with the first alignment marks fails because of insufficient reflectance, the second alignment is performed with the second alignment marks including aluminum. According to this method, both advantages of the poly silicon and the aluminum are provided and the number of required processes is effectively reduced, keeping a decent success rate of the alignment.
However, according to the above conventional technique, when the multi-die alignment fails and the process for changing into the single-die alignment is performed, if the chips in the predetermined area are minute, for example, in a case where hundreds of the chips are included in the predetermined area, the single-die alignment takes hundreds of times longer than does the multi-die alignment to succeed, which causes a problem of time loss. Furthermore, in recent years, the size of the chips processed by the laser trimming tends to become smaller and the number of the chips processed by the laser trimming in the same area tends to increase. In view of this, the time loss in changing into the single-die alignment becomes a problem which cannot be overlooked.
In addition, according to the alignment method disclosed in the Japanese patent publication 2001-35924, it is necessary to produce the semiconductor devices with two kinds of alignment marks including different materials, which causes a problem because the semiconductor fabrication process is made complicated. Moreover, because alternatives to the first alignment marks are only the second alignment marks in the same chips, for example, in case of problems such as a poor reflecting power of the aluminum marks, a break of patterns and an inclination of the substrate in a rough alignment in a previous stage, using the second alignment marks has the same problems as using the first alignment marks and the alignment fails. In particular, if the alignment fails with the second alignment marks, recovering the alignment is impossible and the alignment completely ends in failure.